This invention relates to generation and insertion of forward performance monitoring (xe2x80x9cFwd PMxe2x80x9d) cells during operation and maintenance (xe2x80x9cOAMxe2x80x9d) processing of cell traffic in asynchronous transfer mode (xe2x80x9cATMxe2x80x9d) layer devices.
As shown in FIG. 1, an ATM layer device 10 (everything to the left of network cloud 12) receives ATM cells from any one of a potentially large plurality of input sources 14A, 14B, 14C, 14D, etc. Each input source carries cells corresponding to a potentially large number of ATM connections. ATM layer device 10 processes the received cells and outputs them to network 12 (or to an ATM switch, not shown), by placing each cell in an appropriate one of a number of output queues 16A, 16B, 16C, 16D, etc. corresponding to input sources 14A, 14B, 14C, 14D, etc. As is well known, such processing involves carefully controlled admission of cells from the input sources by access controller 18 so as to avoid head-of-line blocking problems, facilitate proper management of the output buffers, and generally to provide a well-controlled traffic stream. The OAM performance monitoring (xe2x80x9cOAM-PMxe2x80x9d) functionality of ATM layer device 10 (as defined in ITU-T Recommendation I.610xe2x80x94xe2x80x9cB-ISDN Operation and Maintenance Principles and Functionsxe2x80x9d, February 1999, hereafter xe2x80x9cITU-T I.610xe2x80x9d) is represented schematically in FIG. 1 by performance manager (xe2x80x9cPMxe2x80x9d) sub-block 20.
More specifically, FIG. 2 provides an enlarged depiction of ATM layer device 10. For ease of illustration, only three ATM cell input sources 14A 14B, 14C and their corresponding output queues 16A, 16B, 16C are shown. Input source 14A and its corresponding output queue 16A is depicted as currently carrying cells corresponding to connections xe2x80x9c12xe2x80x9d, xe2x80x9c11xe2x80x9d and xe2x80x9c14xe2x80x9d; input source 14B and its corresponding output queue 16B is depicted as currently carrying cells corresponding to connections xe2x80x9c3xe2x80x9d, xe2x80x9c4xe2x80x9d and xe2x80x9c1xe2x80x9d; and, input source 14C and its corresponding output queue 16C is depicted as currently carrying cells corresponding to connection xe2x80x9c7xe2x80x9d. Access controller 18 admits cells from the input sources into processing queue 22, and performs various operations on the cells as they pass through processing queue 22, including identifying the connection each cell belongs to, identifying the PM session associated with that connection, and performing other ATM layer functions such as policing and fault management. PM 20 monitors the cell traffic stream passing through processing queue 22 to output queues 16A, 16B, 16C, and counts the number of cells on each connection.
Periodically, PM 20 inserts a Forward Performance Monitoring (xe2x80x9cFwd PMxe2x80x9d) cell into the cell stream within processing queue 22, as prescribed by ITU-T I.610 and ITU-T Recommendation I.356xe2x80x94xe2x80x9cB-ISDN ATM Layer Cell Transfer Performancexe2x80x9d, October, 1996 (hereafter ITU-T I.356). More particularly, one Fwd PM cell is inserted for every approximately N cells on a connection, where N ranges from 128 to 32768 depending on the data rate of the connection. Because the Fwd PM cells must be inserted based on the number of cells transmitted on a connection, the operation of access controller 18 affects the number of PM cells to be transmitted. Furthermore, other ATM Layer functions (including, for example, cell rate policing as described in ATM Forum TM4.1xe2x80x94ATM Forum Traffic Management Specification Version 4.1, 1999) may affect the number of cells transmitted, thus affecting the number of Fwd PM cells that must be generated. Accordingly, it is convenient to insert the Fwd PM cells at the ATM Layer. However, this poses potential head-of-line blocking problems and/or output queue buffer overflow problems.
For example, output queue 16A depicted in FIG. 3 currently contains three cells (i.e. those labelled xe2x80x9c12xe2x80x9d, xe2x80x9c11xe2x80x9d and xe2x80x9c14xe2x80x9d). This leaves three empty slots (i.e. the three blank, leftmost slots in output queue 16A) into which cells passing through processing queue 22 may be placed. Suppose now that PM 20 determines that it is necessary to insert a Fwd PM cell 24 corresponding to connection xe2x80x9c12xe2x80x9d into the cell stream within processing queue 22. Fwd PM cell 24 is generated by PM 20 and contains, amongst other statistical indicia, a count of the total number of cells corresponding to connection xe2x80x9c12xe2x80x9d which PM 20 has detected passing through processing queue 22 since PM 20 last generated a Fwd PM cell corresponding to connection xe2x80x9c12xe2x80x9d. However, access controller 18 has already admitted into processing queue 22 three cells which are destined for output queue 16A, namely the three cells labelled xe2x80x9c12xe2x80x9d. Thus, there is no room for insertion of Fwd PM cell 24 into processing queue 22 and thence into output queue 16A without dropping one of the three connection xe2x80x9c12xe2x80x9d cells in processing queue 22, which is unacceptable. (After generating and inserting Fwd PM cell 24 as aforesaid, PM 20 clears and restarts its count of the total number of cells corresponding to connection xe2x80x9c12xe2x80x9d.)
The prior art has evolved a variety of solutions to the aforementioned class of head-of-line blocking and/or output queue buffer overflow problems. One such solution, illustrated in FIG. 4, is to provide an access controller 18A and PM 20A adapted to xe2x80x9creservexe2x80x9d a cell slot within output queue 16A into which a Fwd PM cell can be inserted. Specifically, PM 20A signals access controller 18A when PM 20A determines that it is necessary to insert a Fwd PM cell 24A corresponding, for example, to connection xe2x80x9c12xe2x80x9d into the cell stream within processing queue 22. Access controller 18A responds by reserving one of the empty slots in output queue 16A for use by PM 20A. This may necessitate momentarily halting admission of cells from input source 14A into processing queue 22 until space becomes available in output queue 16A. Access controller 18A then signals PM 20A, indicating grant of the reserved slot, and PM 20A reacts by inserting Fwd PM cell 24A into that slot. In practice however, complex timing and logic problems arise, making it difficult to properly implement such a xe2x80x9creservationxe2x80x9d scheme, particularly at high frequencies.
Another prior art solution, illustrated in FIG. 5, is to provide an access controller 18B and PM 20B adapted for xe2x80x9cloop-backxe2x80x9d insertion of Fwd PM cells from PM 20B to access controller 18B. Specifically, when PM 20B determines that it is necessary to insert a Fwd PM cell 24B corresponding, for example, to connection xe2x80x9c12xe2x80x9d into the cell stream within processing queue 22, PM 20B generates Fwd PM cell 24B and transmits cell 24B to an input port of access controller 18B, as indicated at 26 in FIG. 5. Access controller 18B eventually admits cell 24B into processing queue 22. By allowing access controller 18B to handle insertion of cell 24B into processing queue 22, the loop-back technique overcomes the above-described problems of the prior art techniques illustrated in FIGS. 3 and 4. Specifically, access controller 18B does not admit cell 24B into processing queue 22 unless there is room in the appropriate output queue (in this case, output queue 16A) for cell 24B, thereby overcoming the head-of-line blocking and/or output queue buffer overflow problems to which the technique illustrated in FIG. 3 is subject. Furthermore, by allowing access controller 18B to handle insertion of cell 24B into processing queue 22, the loop-back technique avoids the timing and logic problems to which the FIG. 4 xe2x80x9creservationxe2x80x9d technique is subject.
However, the FIG. 5 loop-back technique is subject to a further problem. After generating Fwd PM cell 24B, PM 20B immediately clears and restarts its count of the total number of cells for the corresponding the ATM connection. But, by the time access controller 18B inserts cell 24B into processing queue 22, additional cells corresponding to connection xe2x80x9c12xe2x80x9d may have been admitted into the cell stream within processing queue 22. For example, the two leftmost connection xe2x80x9c12xe2x80x9d cells within processing queue 22 have not yet been xe2x80x9cseenxe2x80x9d by PM 20B, and those two cells have therefore not been included in Fwd PM cell 24B""s count of the total number of connection xe2x80x9c12xe2x80x9d cells. For correct operation, each Fwd PM cell must contain an accurate count of the total number of cells for the corresponding ATM connection which precede the Fwd PM cell. In the example illustrated in FIG. 5, cell 24B""s count of the total number of connection xe2x80x9c12xe2x80x9d cells is two cells less than the correct number, which is unacceptable. Moreover, the next Fwd PM cell generated by PM 20B for connection xe2x80x9c12xe2x80x9d will probably also contain an unacceptably inaccurate count of the total number of connection xe2x80x9c12xe2x80x9d cells, since PM 20B includes the aforementioned two leftmost connection xe2x80x9c12xe2x80x9d cells in the count which it maintains for such next Fwd PM cell, instead of including them in the count maintained for cell 24B.
Yet another prior art solution (not shown) is to permanently reserve room in each output queue into which a predefined number of Fwd PM cells can be inserted. ATM layer device 10 is then configured such that Fwd PM cells are generated only if there is room for them in the reserved space of the appropriate output queue. This solution works, but wastes an unacceptably large amount of expensive output queue buffer space in ATM systems having many input sources and output queues.
The present invention provides an easily implemented, inexpensive Fwd PM cell generation and insertion technique which overcomes the aforementioned deficiencies of the prior art and conforms to the order-dependant requirements of performance monitoring in high-bandwidth, multi-queue ATM layer devices.
The invention facilitates insertion of forward performance monitoring cells into a processing queue coupled to an access controller. A plurality of ATM cell input sources are coupled to the access controller. Each input source supports a plurality of ATM connections. The access controller controllably admits cells from the input sources into the processing queue. The cells are output from the processing queue on one of a plurality of output queues. Each forward performance monitoring cell contains statistical information, including a count of the cells which correspond to one of the ATM connections and which are output through the processing queue. The processing queue is monitored to detect and maintain, for each ATM connection, a count of the total number of cells which pass through the processing queue and which correspond to that ATM connection. In accordance with the invention, before a forward performance monitoring cell corresponding to a particular ATM connection is inserted into the processing queue, an interim cell corresponding to that ATM connection is first transmitted to the access controller, which controllably admits the interim cell into the processing queue. The processing queue is monitored to detect the presence of the interim cell in the processing queue, without interrupting maintenance of the aforementioned counts for the respective ATM connections. Then, while the interim cell remains within the processing queue, the count for the ATM connection corresponding to that interim cell is stored in the interim cell, thereby converting the interim cell into the desired forward performance monitoring cell.